匿名
发表于 2023-4-14 09:13:53
|阅读模式
module div_16 (clk_in, reset, clk_out);
input clk_in;
input reset;
output clk_out;
reg clk_out;
reg [2:0] cnt;
always @(posedge clk_in)
begin
if (!reset) begin
cnt <= 0;
clk_out <= 0;
end
else if (cnt == 7) begin
cnt <= 0;
clk_out <= !clk_out;
end
else begin
cnt <= cnt+1;
clk_out <= clk_out;
end
end
endmodule |
|
